1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device capable of detecting a defect of a column selection line.
2. Description of Related Art
A semiconductor memory represented by DRAM (Dynamic Random Access Memory) is subjected to various operation tests at a manufacturing stage. As one of most important tests among these, there is a detection test of a defective address performed in a wafer state. Most of defective addresses are caused by a defect of a word line or a bit line. Therefore, detected defective addresses can be relieved by replacing the defective line with an auxiliary word line or auxiliary bit line.
However, although it is rare, among defective addresses, some defects are caused by a defect of a column selection line. When there is a defect in a column selection line, all bit lines that may be selected by this column selection line become defective. Therefore, a chip having such a defect basically needs to be discarded.
In a detection test of a defective address, a comparison result is compressed within a chip to shorten a testing time (see Japanese Patent Application Laid-open No. 2000-132998). Compressing a comparison result means to arrange plural comparison results obtained by comparing plural pieces of read data with an expected value, into a one-bit compressed determination signal. When the determination signal indicates a defect, it is recognized that at least one bit of corresponding plural pieces of read data does not match the expected value. This means that how many bits of read data do not match the expected value cannot be known at this stage, even when the determination signal indicates a defect. Consequently, as a typical example, when plural bits of read data are collectively defective such as when there is a defect in a column selection line, this defect cannot be distinguished from a normal bit-line defect even when all bits of data read by the column selection line are defective.
Because a chip having a defect in a column selection line cannot have an address correctly relieved even when a bit line is replaced, the chip is eliminated in a selection test after packaging. Consequently, although the chip will not be mistakenly shipped as a good product, its packaging cost becomes wasteful.
The above problem can occur in all semiconductor devices having a memory area, not only in a semiconductor memory such as a DRAM.